The present invention relates to a field effect transistor and a fabrication method thereof, a semiconductor device and a fabrication method thereof, a logic circuit including the semiconductor device, and a semiconductor substrate, and particularly to a field effect transistor in which a source/a drain are formed in a silicon layer having a strain effect and a fabrication method thereof, a semiconductor device including the field effect transistor and a fabrication method thereof, a logic circuit including the semiconductor device, and a semiconductor substrate on which the field effect transistor, the semiconductor device, or the logic circuit is formed.
With the advance of a technique of forming a thin film made from a group IV semiconductor material such as silicon/silicon germanium, devices using materials having a strain effect have been allowed to be fabricated, and at present, studies are being extensively made to realize high function and low-voltage devices using materials having a strain effect.
The strain effect means a phenomenon that in a thin film semiconductor applied with a stress, an energy band is distorted to change an effective mass of carriers. A semiconductor thin film having such a strain effect has been allowed to be realized by forming a multi-layered film such as silicon/silicon germanium in such a manner as to control an inner stress of the film using a molecular beam epitaxy technique or an ultra-high vacuum chemical vapor deposition (UHV-CVD) process. High quality MOS based devices or sensors have been also developed by controlling a difference in band gap or a film strain through hetero-junction.
A silicon film on a SOI (Silicon on Insulator) substrate formed using a technique of forming a single crystal silicon film by zone melting or irradiation of argon ion laser is applied with a tensile stress. Besides, a silicon film on a SOS (Silicon on Sapphire) substrate is applied with a compressive stress. As a result, for the former silicon film, the mobility of electrons becomes larger and for the latter silicon film, the mobility of positive holes becomes larger. In other words, for the former, the mobility of positive holes becomes smaller and for the latter, the mobility of electrons becomes smaller
For a silicon based MOS (Metal-Oxide-Semiconductor) transistor, by depositing a silicon film on an epitaxial layer made from silicon germanium whose stress is relaxed, the mobility of electrons is made larger by a tensile stress (which is strictly explained such that six regenerated bands are divided into two bands different in effective mass of electrons). Besides, in the case of formation of silicon germanium containing germanium in a large amount (that is, a germanium rich silicon germanium), the mobility of positive holes are made larger by a compressive stress.
In a MOS transistor prepared such that the stress of a channel layer is controlled by forming a multi-layered film based on the above property of the strain effect silicon layer, a high mutual conductance [gm (mobility)] can be obtained. Such a p-type MOS is disclosed in Appl. Phys. Letter (USA), 63 (1993) K.Ismail et al., p660 and IEEE Electronic Devices (USA), 43 (1996) L. H. Jiang and R. G. Elliman, p97. Further, an nMOS is disclosed in Appl. Phys. Letter (USA), 64 (1994) K. Ismail et al., p3124 and IEDM 94-37 (USA), (1994) J. Welser et al.
A pass-transistor, as the advanced high performance logic operable at a low voltage, has been proposed in the field of the advanced applied technology such as a CPU (Central Processing Unit) or MPEG (Moving Picture Experts Group). In such a logic circuit, an nMOS transistor as a main component requires such a high level characteristic as to exhibit a high mutual conductance with a low voltage operation. Besides, a pMOS transistor is used for pre-charge or the like and has less number of elements. That is, the pMOs transistor does not require a higher operational speed as compared with the nMOS, and therefore, it is not disadvantageous from the real viewpoint even if the performance is determined by adjustment of the channel width W.
In the case where the above-described related art pMOS or nMOS transistor is used in an application requiring a high performance at a low voltage, however, there occurs a problem of a junction leak of the transistor because the junction of the source/drain is positioned in a silicon germanium layer having a small band gap or formed at an interface of silicon/silicon germanium.
An object of the present invention is to solve the above-described problem and to provide a field effect transistor and a fabrication method thereof, a semiconductor device and a fabrication method thereof, a logic circuit including the semiconductor device, and a substrate, in which the junction of a source/a drain is formed in a strain effect silicon layer for suppressing occurrence of a junction leak of the transistor.
To achieve the above object, according to a first aspect of the present invention, there is provided a field effect transistor formed in a silicon layer as a semiconductor layer having a strain effect (hereinafter, referred to as xe2x80x9ca strain effect silicon layer) formed in an upper layer of a semiconductor substrate, the field effect transistor including: a source/a drain formed only in the semiconductor layer having the strain effect.
In this field effect transistor, since the source/drain are formed only in the strain effect silicon layer, the junction of the source/drain is present in the strain effect silicon layer, to improve the mobility of the transistor and suppress occurrence of a junction leak of the transistor, thereby improving the performance of the transistor.
According to a second aspect of the present invention, there is provided a method of fabricating a field effect transistor, including the steps of: forming a semiconductor substrate in such a manner that a strain effect silicon layer is formed in an upper layer of the semiconductor substrate; forming a gate electrode on the strain effect silicon layer through a gate insulating film; and forming a source/a drain by doping an impurity for forming the source/drain in the strain effect silicon layer on both sides of the gate electrode.
In this method of fabricating a field effect transistor, since the source/drain of the field effect transistor are formed only in the strain effect silicon layer, the junction of the source/drain is formed in the strain effect silicon layer, to thereby suppress occurrence of a junction leak of the transistor.
According to a third aspect of the present invention, there is provided a semiconductor device including: a p-channel type field effect transistor and an n-channel type field effect transistor both formed in a strain effect silicon layer formed in an upper layer of a semiconductor substrate, wherein a source/a drain of the p-channel type field effect transistor and a source/a drain of the n-channel type field effect transistor are formed only in the strain effect silicon layer.
In this semiconductor device, since each source/drain of the p-channel type and n-channel type field effect transistors are formed only in the strain effect silicon layer, the junction of the source/drain is present in the strain effect silicon layer, to thereby suppress occurrence of a junction leak of the transistor.
The above semiconductor device also has a structure being substantially similar to a related art CMOS structure because each source/drain of the p-channel type and n-channel type transistors are formed in one strain effect silicon layers. As a result, the structure of the semiconductor device is simplified.
According to a fourth aspect of the present invention, there is provided a method of fabricating a semiconductor device, including the steps of: forming a semiconductor substrate in such a manner that a strain effect silicon layer is formed in an upper layer of the semiconductor substrate; forming a gate electrode of a p-channel type field effect transistor and a gate electrode of a n-channel type field effect transistor on the strain effect silicon layer through a gate insulating film; forming a source/a drain composed of p-type diffusion layers in the strain effect silicon layer on both sides of the gate electrode of the p-channel type field effect transistor; and forming a source/a drain composed of n-type diffusion layers in the strain effect silicon layer on both sides of the gate electrode of the n-channel type field effect transistor.
In this method of fabricating a semiconductor device, since each source/drain of the p-channel type and n-channel type field effect transistors are formed only in the strain effect silicon layer, the junction of each source/drain is formed only in the strain effect silicon layer, to thereby suppress occurrence of a junction leak in each source/drain.
In this method, since each source/drain are formed in one strain effect silicon layer, it is possible to eliminate the need of provision of a channel forming layer corresponding to each source/drain, and hence to simplify the fabrication process.
According to a fifth aspect of the present invention, there is provided a logic circuit including: a semiconductor device having a p-channel type field effect transistor and an n-channel type field effect transistor; wherein a semiconductor substrate on which the logic circuit is formed includes a semiconductor substrate in which a silicon layer having a strain effect is formed in an upper layer thereof; a source/a drain of the p-channel type field effect transistor are formed only in the silicon layer having the strain effect; and a source/a drain of the n-channel type field effect transistor are formed only in the silicon layer having the strain effect.
In this logic circuit, since each source/drain of both the field effect transistors are formed only in the strain effect silicon layer formed in the upper layer of the semiconductor substrate, the junction of each source/drain is present in the strain effect silicon layer, to improve the mobility of each transistor and suppress occurrence of a junction leak of the transistor, thereby improving the performance of each transistor.
The semiconductor device formed in the above logic circuit has a structure being substantially similar to a related art CMOS structure because each source/drain of the p-channel type and n-channel type transistors are formed in one strain effect silicon layers. As a result, the structure of the semiconductor device is simplified.
According to a sixth aspect of the present invention, there is provided a semiconductor substrate including: a germanium base; a relax layer formed on the germanium base, the relax layer being composed of a silicon germanium layer whose stress is relaxed; and a silicon formed on the relax layer, the silicon layer having a strain effect.
In this semiconductor substrate, since the base is formed of the germanium base, the relax layer composed of the silicon germanium layer whose stress is relaxed can be formed not through a buffer layer but directly on the germanium base. To be more specific, since there is less possibility of occurrence of lattice mismatching between the germanium base and the relax layer, the above configuration can be adopted.
The above configuration makes it possible to simplify the structure of the semiconductor substrate and hence to simplify the process of forming the semiconductor substrate.